1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device which erases data of memory cells all at once, and particularly, for an NOR type flash memory, a non-volatile semiconductor memory device in which data of the memory cells is over-erased so as to give rise to problems.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98
Recently, a flash memory is mainly used as a non-volatile semiconductor memory device in which data can be electrically written into and erased from the memory cell. The flash memory can erase data of the memory cells all at once for each block (which is also called a xe2x80x9csectorxe2x80x9d) composed of memory cells of all or a part of a memory cell array.
In a flash memory, electrons are injected into a floating gate of the memory cell in order to write into the memory cell or are extracted from the floating gate of the memory cell in order to erase from the memory cell. Since a threshold voltage of the memory cell is varied depending on the amount of electric charge accumulated in the floating gate, using this property, when electrons are injected into the floating gate and the threshold voltage reaches a high level (writing state) for example, this condition corresponds to a logic value of xe2x80x9c0xe2x80x9d. On the other hand, when electrons are extracted from the floating gate and the threshold voltage reaches a low level (erasing state) for example, this condition corresponds to a logic value of xe2x80x9c1xe2x80x9d.
However, the erasing speed depends on each memory cell because of the variation in the quality such as the thickness of the oxide film of the transistors composing the memory cells, or minor defects. Even if the data of the memory cells is erased using the same method, the threshold voltages of every memory cell are not uniform and the threshold voltage has a predetermined distribution in view of the memory cells as a whole. If batch erasing is performed until reaching the threshold voltage for the memory cells having a slow erasing speed, the batch erasing will be excessively performed for the memory cells having a fast erasing speed. A memory cell in which data is over-erased is called xe2x80x9ca memory cell having deep depletionxe2x80x9d or xe2x80x9ca memory cell having a depletion defectxe2x80x9d. Such memory cells in which data is over-erased generate various problems; therefore, it is required that the presence of these memory cells be completely eliminated.
A flash memory utilizing a countermeasure for memory cells having deep depletion is disclosed in, for example, Japanese Unexamined Patent Application No. Hei 8-106793 (hereinafter, referred to as JP 8-106793). In this application, erasing the data of the memory cell in an erasure block is performed as follows. A memory cell having a low threshold voltage, logic value xe2x80x9c1xe2x80x9d, is detected and is written until reaching a high threshold voltage, logic value xe2x80x9c0xe2x80x9d, so that every memory cell in the erasure block has a high threshold voltage, logic value xe2x80x9c0xe2x80x9d. Next, the data of all memory cells in the erasure block is erased all at once so that each memory cell has a logic value xe2x80x9c1xe2x80x9d. The data of the memory cells is erased so that the upper limit of the threshold voltage of each memory cell is the predetermined xe2x80x9cerase verify voltagexe2x80x9d.
As described above, when the batch erasing is performed, memory cells having deep depletion are generated in which the threshold voltage is negative due to the variations in the erasing speeds of each memory cell. The voltage of a word line applied to a control gate of the memory cell is set to xe2x80x9c0 Vxe2x80x9d, and memory cells having deep depletion are detected and rewritten so as not to be in depletion. Because it is not known which memory cells connected to a digit line (which is also referred to a bit line, a data line, or the like) have deep depletion, the rewrite is performed for each digit line and not for each memory cell.
Therefore, shallow writing is performed in every memory cell connected to the digit line, verifying is performed to detect whether depletion is not in the digit line, and shallow rewriting is repeated until the data of memory cells in the digit line having deep depletion is completely erased. The voltage of the word line is set to xe2x80x9c1.2 Vxe2x80x9d and rewriting and verifying are performed for each memory cell, in the same way that xe2x80x9c0 Vxe2x80x9d is applied to the word line, in order to rewrite memory cells having latent deep depletion.
However, in the flash memory disclosed in the above-mentioned document JP 8-106793, the following problems arises.
FIG. 8 shows graphs explaining this problem, and shows the threshold voltage distribution for memory cells as a whole in the erasure block. The X-axes show the number of memory cells N for each threshold voltage, and the Y-axes show the threshold voltages Vtm of the memory cells. The graph on the left in FIG. 8 shows the actual distributions of the threshold voltage. The distribution indicated by a reference letter D1 shows memory cells having deep depletion, and the distribution indicated by a reference letter D2 shows normally erased memory cells having no depletion.
Furthermore, the graph in the center of FIG. 8 shows the apparent distributions of the threshold voltage. The distribution of normally erased memory cells indicated by a reference letter D3 seems to be at lower position than distribution D2 shown in the graph on the left. This is caused by the existence of memory cells having deep depletion shown in distribution D1. The will be explained as follows. FIG. 9 is a partial diagrammatic view of a flash memory. A digit line 100 is one of the digit lines composing the memory cell array. A sense amplifier 101 senses a memory data of the memory cell connected to digit line 100 by comparing an amount of electric current of a current Id passing through digit line 100 with an amount of electric current of a predetermined reference electric current.
Furthermore, each of the memory cells 102 to 104 is a part of the memory cells connected to the digit line 100. Word lines 105 to 107 are signal lines for selecting these memory cells 102 to 104. Electric currents Ic1 to Ic3 are currents passed between the drain sources of memory cells 102 to 104, respectively. Memory cells 102 and 103 are in a writing state and memory cell 104 is a memory cell having deep depletion. To determine the threshold voltage of memory cell 102, a predetermined voltage is applied to word line 105, and word lines 106 and 107 and other word lines (not shown) are set to xe2x80x9c0Vxe2x80x9d.
In contrast, if memory cell 104 is not a memory cell having deep depletion, as long as the above predetermined voltage applied to word line 105 does not reach the threshold voltage of memory cell 102, memory cell 102 will remain OFF and the amount of electric current Ic1 is approximately xe2x80x9c0xe2x80x9d. Since electric current is not applied to word lines other than word line 105, the amounts of electric current Ic2 and Ic3 are approximately xe2x80x9c0xe2x80x9d. Therefore, the amount of electric current Id becomes approximately xe2x80x9c0xe2x80x9d. On the other hand, when the predetermined voltage applied to word line 105 is equal to or greater than the threshold voltage of memory cell 102, memory cell 102 turns ON. Subsequently, electric current Ic1, depending on the characteristics of memory cell 102, flows, and electric current Id equals electric current Ic1 since the amounts of electric currents Ic2 and Ic3 are xe2x80x9c0xe2x80x9d. Therefore, sense amplifier 101 senses the amount of electric current Id to determine whether the threshold voltage of memory cell 102 is equal to or greater than the predetermined voltage.
However, if memory cell 104 is a memory cell having deep depletion, for example, when memory cell 102 is read, even if the actual data stored in each memory cell is xe2x80x9c0xe2x80x9d, an error reading may occur as if the data stored in the memory cell was xe2x80x9c1xe2x80x9d. Since the threshold voltage of memory cell 104 having deep depletion is less than xe2x80x9c0 Vxe2x80x9d, a considerable amount of electric current Ic3 flows even if the voltage to be applied to word line 107 is xe2x80x9c0 Vxe2x80x9d. Therefore, when memory cell 102 is chosen, the amount of electric current Id is the sum of electric currents Ic1 and Ic3.
Memory cells 102, 103, and the like which are connected to the digit lines and are identical to the memory cells in which data is over-erased, are read, such that the amount of electric current Id apparently increases. If the voltages applied to the control gates of the memory cells are the same, the amount of the electric current passing through each memory cell increases as the threshold voltage of the memory cell decreases. Therefore, an apparent increase in the amount of electric current Id is equivalent to an apparent decrease in the threshold voltage of memory cell 102. Similarly, this occurs in other memory cells; therefore, the threshold voltage distributions of all memory cells of the erasure block, as mentioned above, seem to be distributions which are as a whole at a lower position than the positions of the actual distributions.
If the additional amount of electric current Ic3 is large, the amount of electric current Id exceeds the amount of the reference electric current. Therefore, a problem arises wherein memory cell 102 actually has a data value of xe2x80x9c0xe2x80x9d which specifies a high threshold voltage but memory cell 102 apparently has a data value of xe2x80x9c1xe2x80x9d which specifies a low threshold voltage. To prevent such an error reading, the memory cell having deep depletion is rewritten to eliminate the over-erase condition and restore the normal erase condition. However, in conventional flash memory, further problems arises in the rewriting process as follows.
If the threshold voltage distribution is apparently at a low position due to memory cells having deep depletion, when memory cells having a threshold voltage whose level is equal to or greater than a xe2x80x9crewrite determination levelxe2x80x9d as shown in FIG. 8 are rewritten, memory cells of the distribution D3 having a threshold voltage whose level is less than the rewrite determination level are normally erased. Therefore, the rewrite is not required. However, in actuality, memory cells having a threshold voltage whose level is less than the rewrite determination level are rewritten. Since the rewrite for the memory cells cannot be performed simultaneously with the erasure, the rewrite is performed per each memory cell unit. Therefore, for rewriting of the memory cells in which rewriting is not actually required, the process time for the erasure process as a whole increases.
Furthermore, when the rewrite is performed for the distribution shown in the center of FIG. 8, threshold voltage distributions D1 and D3 of the memory cells become the distributions D4 and D5 shown on the right in FIG. 8. In the erasing operation, the threshold voltages of all the memory cells of the erasure blocks need to be equal to or less than an xe2x80x9cerase determination levelxe2x80x9d (shown on the right in FIG. 8). The threshold voltage of distribution D5 increases above the xe2x80x9cerase determination levelxe2x80x9d. In order to be equal to or less than the xe2x80x9cerase determination levelxe2x80x9d for the memory cells of distribution D5, the erasure needs to be performed again. Therefore, the process time for the erasure process as a whole further increases. If memory cells having deep depletion are generated due to the erasure again, the rewrite is required again. Depending on the conditions, there is a possibility that the erasure and the rewrite may be repeated endlessly.
Moreover, if there are memory cells having deep depletion, the distribution of the threshold voltage is, as a whole, extended as shown in the distributions D4 and D5. Therefore, when the verify which detects whether the threshold voltage of the memory cell during the rewrite is equal to or greater than the xe2x80x9crewrite determination levelxe2x80x9d is performed, a problem arises wherein read margin may not sufficiently remain. Therefore, memory cells having deep depletion are removed beforehand, and the width of the threshold voltage distribution is reduced to leave sufficient read margins.
Additionally, in order to obtain transistors with pressure drop resistance, low electric power consumption, and high speed, due to miniaturization, are fined in recent years, various semiconductor devices comprising a non-volatile semiconductor memory have been changing to devices having a low power-supply voltage operation. The threshold voltage of the memory cells needs to be decreased and the threshold voltage distribution of the memory cells needs to be narrow at the same time in order to achieve low power-supply voltage operation. However, since the original threshold voltage distribution of the memory cells is determined according to the manufacturing process, it is not easy to make improvements by decreasing the threshold voltage in the manufacturing process. Therefore, it is describe that circuit operations, such as the erasing operation, be improved without modifying the manufacturing process in order to essentially narrow the threshold voltage distribution.
In light of the above problems, the object of the present invention is to provide a non-volatile semiconductor memory in which unnecessary rewrites are not performed even when there are memory cells having deep depletion, and in which the process time for the erasure process as a whole is not increased by increasing the number of rewrites. Furthermore, another object of the present invention is to provide a non-volatile semiconductor memory in which a sufficient read margin is remains and the memory is suitable for low power-supply voltage operation by narrowing the width of the threshold voltage distribution of the memory cells as much as possible.
To solve the above-mentioned problems, a first aspect of the present invention is a non-volatile semiconductor memory comprising a non-volatile memory cell which is capable of being written to and totally erased electrically and in which a threshold voltage distribution of the memory cell is affected by memory cells in which data is over-erased, wherein the memory is provided with: a first erasing means for totally erasing erasable memory cells, a first rewriting means for rewriting memory cells in which data is over-erased by totally erasing while simultaneously verifying each memory cell, a second erasing means for erasing memory cells which were not erased up to a desired erase determination level after the first rewrite, and a second rewriting means for rewriting memory cells which were not rewritten up to a desired rewrite determination level while simultaneously verifying each memory cell after the second erase.
A second aspect of the present invention is a non-volatile semiconductor memory comprising a non-volatile memory cell which is capable of being written to and totally erased electrically and in which a threshold voltage distribution of the memory cell is affected by the memory cell in which data is over-erased, wherein the memory is provided with: a first erasing means for totally erasing erasable memory cells up to a first erase determination level which is higher than a desired erase determination level, a first rewriting means for rewriting memory cells in which data is over-erased by totally erasing up to a first rewrite determination level lower than a desired rewrite determination level while simultaneously verifying for each memory cell, a second erasing means for erasing memory cells which were not erased up to the desired erase determination level after the first rewrite, and a second rewriting means for rewriting memory cells which were not rewritten up to the desired rewrite determination level while simultaneously verifying each memory cell after the second erase.
According to the first and second aspects of the present invention, if the threshold voltage distribution seems to be in a lower position owing to the memory cells in which data is over-erased, memory cells which do not need to be rewritten are not rewritten. Only the memory cells to be rewritten are rewritten and excessive rewrites do not occur, therefore, the process time for the total erasure process can be shortened in comparison to the conventional process time. Furthermore, since the width of the threshold voltage distribution can be narrowed more than the conventional width of a threshold voltage distribution, sufficient read margins remain and a non-volatile semiconductor memory which is suitable for low power-supply voltage operation can be obtained with no additional manufacturing processes or the like.
A third aspect of the present invention is a non-volatile semiconductor memory according to the second aspect, wherein the first erase determination level may be set higher than the desired erase determination level for an amount of increased voltage when the threshold voltage of the memory cells not erased excessively increases during rewriting by the first rewriting means.
Furthermore, in the second aspect of the present invention, data in the memory cells is erased up to the first erase determination level which is higher than the desired erase determination level when data in the memory cells is totally erased. According to the third aspect of the present invention, to perform this erasure, as shown in the third aspect of the present invention, for example, for the case where the amount of increased voltage when the threshold voltage of the memory cells in which data is not over-erased increases by rewriting the memory cells in which data is over-erased, the first erase determination level may be set higher than the desired erase determination level. Accordingly, the memory cells having a threshold voltage between the desired erase determination level and the first erase determination level can be totally rewritten when the second rewrite is performed.
A fourth aspect of the present invention is a non-volatile semiconductor memory comprising a non-volatile memory cell which is capable of being written to and totally erased electrically and in which a threshold voltage distribution of the memory cell is effected by memory cells in which data is over-erased, wherein the memory is provided with: an erasing means for totally erasing erasable memory cells up to a desired erase determination level, a first rewriting means for rewriting memory cells in which data is over-erased by totally erasing up to a first rewrite determination level lower than a desired rewrite determination level while simultaneously verifying each memory cell, and a second rewriting means for rewriting memory cells not rewritten up to the desired rewrite determination level while verifying for each memory cell after the first rewrite.
According to the fourth aspect of the present invention, the effects of the first and second aspects can be obtained as well, and the erasure may be performed once. Therefore, the control for erasing can be simplified and the process time for the total erasure process can be shortened in comparison to the conventional process time.
A fifth aspect of the present invention is a non-volatile semiconductor memory according to any one of the second to fourth aspects, wherein the first rewrite determination level may be set lower than the desired rewrite determination level for an amount of increased voltage when the threshold voltage of the memory cells in which data is not over-erased increases during rewriting by the first rewriting means.
Furthermore, according to the second and fourth aspects of the present invention, the first rewrite is performed up to the rewrite determination level which is lower than the desired rewrite determination level. To perform this rewriting, as shown in the fifth aspect of the present invention, for example, when the amount of increased voltage when the threshold voltage of the memory cells in which data is not over-erased increases by rewriting the memory cells in which data is over-erased, the first rewrite determination level may be set lower than the desired rewrite determination level used when the first erase is performed. Therefore, there is no effect such as that the threshold voltage distribution seems to decrease due to the memory cells in which data is over-erased and only the memory cells to be rewritten are rewritten.
A sixth aspect of the present invention is a non-volatile semiconductor memory according to any one of the first to fifth aspects, wherein a rewrite control voltage to be applied to the memory cells when the first rewrite determination means is performed is higher than a rewrite control voltage to be applied to the memory cells when the second rewrite determination means is performed.
According to the sixth aspect of the present invention, the rewrite control voltage which is applied to the memory cell for the first rewrite is higher than the rewrite control voltage for the second rewrite. Therefore, the number of times for writing when the memory cells having deep depletion are rewritten by the first rewrite can be decreased, and the erase current for the rewriting can be reduced.
A seventh aspect of the present invention is a non-volatile semiconductor memory according to any one of the first to sixth aspects, wherein a read control voltage for verifying to be applied to the memory cells when verifying while rewriting is higher than a read control voltage to be applied during normal reading by the first rewriting means or the second rewriting means.
According to the seventh aspect of the present invention, when verifying is performed in the first rewriting, the read control voltage which is applied to the memory cells is higher than the read control voltage when normally reading. Therefore, the amount of current which flows in the memory cells for verifying can be increased. As a result, the effect of the leakage current flowing into the memory cells in which data be over-erased can be almost ignored, and the memory cells which are in the depletion state and require rewriting can be more accurately determined.
A eighth aspect of the present invention is a non-volatile semiconductor memory according to any one of the first to seventh aspects, wherein the first rewriting means or the second rewriting means detects, for each digit line, whether there are memory cells in which data is over-erased in the digit line for rewriting, and verifies and rewrites the digit line for each memory cell only when the there are memory cells in which data is over-erased.
According to the eighth aspect of the present invention, after detecting whether there are memory cells in the digit line in which data is over-erased, the digit line is verified and rewritten for each memory cell. For digit lines which are not connected to the memory cells in which data is over-erased, it is not necessary to determine whether a rewrite for each memory cell is required. Therefore, the time for the process can be reduced.
A ninth aspect of the present invention is a non-volatile semiconductor memory according to any one of the first to eighth aspects, wherein the first rewriting means or the second rewriting means rewrites the memory cells which are to be rewritten to the mean of the threshold voltage distribution of the memory cells in which data is not over-erased.
According to the ninth aspect of the present invention, the data of the memory cells for rewriting is rewritten around the mean value of the threshold voltage distribution of the memory cells in which data is not over-erased. As a result, the threshold voltage distribution can have a peak voltage and keep its shape. Furthermore, when the second erase operation is performed, the probability that data of the memory cells is in the depletion state can be decreased.
A tenth aspect of the present invention is a non-volatile semiconductor memory comprising a non-volatile memory cell which is capable of being written to and totally erased electrically and in which a threshold voltage distribution of the memory cell is affected by data in memory cells in which data is over-erased, wherein only the memory cells in which data is over-erased are detected in memory cells for erasure and rewritten to a desired threshold voltage, and then further rewritten to a desired threshold voltage distribution.
According to the tenth aspect of the present invention, only memory cells in which data is over-erased are detected, are rewritten up to the predetermined threshold voltage distribution, and further, are rewritten up to the desired threshold voltage distribution. As a result, the effects of the first and second aspects can be obtained as well.
An eleventh aspect of the present invention is a non-volatile semiconductor memory comprising a non-volatile memory cell which is capable of being written to and totally erased electrically and in which a threshold voltage distribution of the memory cell is affected by data in memory cells in which data is over-erased, wherein a threshold voltage distribution of memory cells for erasure, which seems to be at lower position owing to the memory cells in which data is over-erased is restored to an actual threshold voltage distribution and then rewritten to a desired threshold voltage distribution.
According to the eleventh aspect of the present invention, the threshold voltage distribution which seems to be at lower position owing to the memory cells in which data is over-erased is restored to the actual threshold voltage distribution and then rewritten up to the desired threshold voltage distribution. As a result, the effects of the first and second aspects can be obtained as well.